I. Field of the Invention
The present invention relates to the field of electronic circuitry, and in particular to multi-layer circuit assemblies such as chip scale packages, and the preparation thereof.
II. Technical Considerations
Electrical components, for example, resistors, transistors, and capacitors, are commonly mounted on circuit panel structures such as printed circuit boards. Circuit panels ordinarily include a generally flat sheet of dielectric material with electrical conductors disposed on a major, flat surface of the sheet, or on both major surfaces. The conductors are commonly formed from metallic materials such as copper and serve to interconnect the electrical components mounted to the board. Where the conductors are disposed on both major surfaces of the panel, the panel may have via conductors extending through holes (or “through vias”) in the dielectric layer so as to interconnect the conductors on opposite surfaces. Multi-layer circuit panel assemblies have been made heretofore which incorporate multiple stacked circuit panels with additional layers of dielectric materials separating the conductors on mutually facing surfaces of adjacent panels in the stack. These multi-layer assemblies ordinarily incorporate interconnections extending between the conductors on the various circuit panels in the stack as necessary to provide the required electrical interconnections.
In microelectronic circuit packages, circuits and units are prepared in packaging levels of increasing scale. Generally, the smallest scale packaging levels are typically semiconductor chips housing multiple microcircuits and/or other components. Such chips are usually made from ceramics, silicon, and the like. Intermediate package levels (i.e., “chip carriers”) comprising multi-layer substrates may have attached thereto a plurality of small-scale chips housing many microelectronic circuits. Likewise, these intermediate package levels themselves can be attached to larger scale circuit cards, motherboards, and the like. The intermediate package levels serve several purposes in the overall circuit assembly including structural support, transitional integration of the smaller scale microcircuits and circuits to larger scale boards, and the dissipation of heat from the circuit assembly. Substrates used in conventional intermediate package levels have included a variety of materials, for example, ceramic, fiberglass reinforced polyepoxides, and polyimides.
The aforementioned substrates, while offering sufficient rigidity to provide structural support to the circuit assembly, typically have thermal coefficients of expansion much different than that of the microelectronic chips to be attached to them. As a result, failure of the circuit assembly after repeated use is a risk due to failure of adhesive joints between the layers of the assembly.
Likewise, dielectric materials used on the substrates must meet several requirements, including conformality, flame resistance, and compatible thermal expansion properties. Conventional dielectric materials include, for example, polyimides, polyepoxides, phenolics, and fluorocarbons. These polymeric dielectrics typically have thermal coefficients of expansion much higher than that of the adjacent layers.
There has been an increasing need for circuit panel structures which provide high density, complex interconnections. Such a need can be addressed by multi-layer circuit panel structures, however, the fabrication of such multi-layer circuit assemblies has presented serious drawbacks.
Generally multi-layer panels are made by providing individual, dual sided circuit panels including appropriate conductors. The panels are then laminated one atop the other with one or more layers of uncured or partially cured dielectric material, commonly referred to as “prepregs” disposed between each pair of adjacent panels. Such a stack ordinarily is cured under heat and pressure to form a unitary mass. After curing, holes typically are drilled through the stack at locations where electrical connections between different boards are desired. The resulting holes or “through vias” are then coated or filled with electrically conductive materials usually by plating the interiors of the holes to form a plated through via. It is difficult to drill holes with a high ratio of depth to diameter, thus the holes used in such assemblies must be relatively large and consume a great deal of space in the assembly.
U.S. Pat. No. 6,266,874 B1 discloses of method of making a microelectronic component by providing a conductive substrate or “core”; providing a resist at selected locations on the conductive core; and electrophoretically depositing an uncured dielectric material on the conductive core except at locations covered by the resist. The reference suggests that the electrophoretically deposited material can be a cationic acrylic- or cationic epoxy-based composition as those known in the art and commercially available. The electrophoretically deposited material then is cured to form a conformal dielectric layer, and the resist is removed so that the dielectric layer has openings extending to the conductive core at locations which had been covered by the resist. The holes thus formed and extending to the coated substrate or “core” are commonly referred to as “blind vias”. In one embodiment, the structural conductive element is a metal sheet containing continuous through holes or “through vias” extending from one major surface to the opposite major surface. When the dielectric material is applied electrophoretically, the dielectric material is deposited at a uniform thickness onto the conductive element surface and the hole walls. It has been found, however, that the electrophoretically deposited dielectric materials suggested by this reference can be flammable, and thus do not meet typical flame retardancy requirements.
U.S. Pat. Nos. 5,224,265 and 5,232,548 disclose methods of fabricating multi-layer thin-film wiring structures for use in circuit assemblies. The dielectric applied to the core substrate is preferably a fully cured and annealed thermoplastic polymer such as polytetrafluoroethylene, polysulfone, or polyimide-siloxane, preferably applied by lamination. Such dielectrics are not necessarily applied as conformal coatings, and may not have dielectric constants or dissipation factors low enough to accommodate the high frequencies of circuit systems currently being designed for the electronics market today. Moreover, dielectric properties of conventional dielectric coatings have been known to degrade at high frequencies.
While the above-identified references disclose through holes (“vias”) in the wiring structures, there is no appreciation in the references of the need for a relatively high via density. High via density allows for a high number of chip connections, as may be required in a highly functional chip scale package for applications such as cellular phones and the like.
It should be noted that high via density in a circuit layer is critical for the operation of a circuit system having a high number of chip connections; however, high via density also contributes to crosstalk. Therefore, a circuit package designed with high via density needs to be fabricated using a very effective dielectric that does not degrade at high frequencies.
U.S. Pat. No. 5,153,986 discloses a method of fabricating metal core layers for a multi-layer circuit board. Suitable dielectrics include vapor-depositable conformal polymeric coatings. The method uses solid metal cores and the reference describes in broad, generic terms circuitization of the substrate. Circuitization of intermediate package levels is conventionally performed by applying a positive- or negative-acting photoresist to the metallized substrate, followed by exposure, development, and stripping to yield a desired circuit pattern. Photoresist compositions are typically applied by laminating, spraying, or immersion. The photoresist layer thus applied may have a thickness of 5 microns to 50 microns.
In addition to the ceramic, fiberglass reinforced polyepoxides, and polyimides mentioned above, conventional substrates used in intermediate package levels further include solid metal sheets such as are disclosed in U.S. Pat. No. 5,153,986. These solid substrates must be perforated during fabrication of the circuit assembly to provide through holes for alignment purposes. Again, while the reference discloses vias in the circuit layers, there is no appreciation of the need for a relatively high via density to accommodate highly functionalized chips.
In view of the prior art processes, it would be desirable to provide a process for preparing a multi-layer circuit assembly that overcomes the drawbacks of the prior art. That is, it would be desirable to provide a process for preparing a multi-layer circuit assembly with high via density to accommodate highly functional components, using an effective dielectric that does not degrade at high frequencies and meets further requirements including conformality and flame resistance.